ULX3S

ULX3S Tiny Tapeout

Turn your FPGA design into an ASIC with Tiny Tapeout.

Use the ulx3s/ttsky-verilog-template as a starting point for your submission (or any of the other TinyTapeout templates).

A working minimal example is the Hazard3-Doom tt-fpga-ulx workflow.

Add a job step such as this to the workflow file:

jobs:
  fpga-ulx3s:
    runs-on: ubuntu-24.04
    steps:
      - name: checkout repo
        uses: actions/checkout@v7
        with:
          submodules: recursive

      - name: FPGA bitstream for TT ASIC Sim (ULX3S ECP5)
        uses: ulx3s/tt-gds-action/fpga/ulx3s@experimental
        with:
          ecp5-device: 85k
          lpf: tt/fpga/ulx3s/ulx3s_v316.lpf
          artifact-name: fpga_ulx3s_ecp5
          uart-enabled: true

For more details, see the Tiny Tapeout Action on GitHub Marketplace.

There’s a bare-bones TT example in the Hazard3-Doom repository:

• info.yaml
• src/project.v
• .github/workflows/tt-fpga-ulx.yaml
• app.tinytapeout.com/projects/6226 (the default name top_module: "tt_um_ulx3s_example" is here in #6226)

[gojimmypi] has a more extensive example in the ttgf-UART-FSM-TRNG-Lab/ulx3s and the fpga-ulx3s-experimental-test.yaml workflow example.

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Chat and support

Discord Channel

• https://discord.gg/qwMUk6W (problems/question/general chat); # tinytapeout

Gitter Channel

• https://gitter.im/ulx3s/Lobby (Focused on development)

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